1. Field of the Invention
The present invention relates to a method for structuring a laterally extending first layer in a semiconductor device with the aid of a reactive second layer, which together with the first layer to be structured forms first reaction products, which are removed by material removal that acts selectively on the first reaction products.
2. Description of the Background Art
In this context, a semiconductor device is understood to mean a wafer, for example. A method is known from U.S. Pat. No. 6,211,044 B1 that is directed to the fabrication of MOS transistors having gate electrodes that are smaller than 0.1 micrometers in width. According to U.S. Pat. No. 6,211,044 B1, such widths cannot be defined reliably even with lithographic methods operating with ultraviolet light. In order to define such widths, first a nitride etch stop layer and then a first metallic reaction layer, and subsequently a layer that is inert relative to the reaction layer, are created on a wafer having a gate layer on a layer series of a dielectric gate layer and a semiconductor substrate.
A hard mask is formed from the reaction layer and the inert layer by lithographic steps, and this hard mask defines a lithography-dependent first width D1 in an etching step. After an etching step, corresponding mesa structures with the width D1 remain on the etch stop layer, which contain material of the first metallic reaction layer. To reduce the structure width, a second reaction layer of polysilicon is deposited, from which reactive spacers on the side walls of the mesa structures are created through an anisotropic etching step. The side walls of the mesa structures are silicidized by a laterally progressing reaction of the spacer material with the material of the first reaction layer, wherein a remaining volume of material of the first reaction layer with width D2<D1, between the silicidized side walls, is not encompassed by the reaction.
A structure width D2 that is reduced in the lateral direction is thus produced by selective etching of the silicide, in which the remaining volume is not removed. The remaining volume subsequently serves as a hard mask for structuring the etch stop layer and the gate layer beneath it.
In fabrication of semiconductor electronic devices and integrated circuits, it can be desirable to remove an existing layer, possibly as a function of location, to a defined depth.
One example is conductive layers of polysilicon that must be locally removed to a defined depth to permit dielectric insulation from conductive layers to be deposited thereon. For example, when a first conductor of polysilicon is deposited over a nitride block, a three-dimensional conductor structure results that is cut into during planarization.
A number of disadvantages arise in back-etching to the depth of the conductor in a dry etching chamber. For example, in the case of semiconductor devices, which have vertical poly conductor edges, long over-etching is necessary to remove the resulting spacers. In addition, undercut conductor edges must be freed from their spacers with the aid of isotropic etching chemistry, which impairs the selectivity of the etching with respect to adjacent dielectrics.
Wet back-etching of a polysilicon conductor does not provide adequate selectivity to oxide, and in the wet methods no endpoint is generally available for controlling the etching when etch stop layers are to be avoided.